The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Memory integrated circuits (ICs) typically include memory arrays of one or more dimensions. For example, a two-dimensional memory array includes rows and columns of memory cells that store binary data bits. A memory cell can be a single-level cell (SLC) or a multi-level cell (MLC). A single-level cell may store one of two states that correspond to one bit (e.g., 0 or 1). A multi-level cell may store one of a plurality of states corresponding to two or more bits. For example, a two-bit multi-level cell may store one of four states, in which each state corresponds to two bits (e.g., 00, 01, 10, or 11). The increased storage capacity of multi-level cells may result in a lower overall cost per byte of storage. NAND flash memory and NOR flash memory are examples of memory systems that include multi-level cells.
Referring now to FIG. 1, a portion of a memory array 10 includes, for example, two-bit MLCs 12-0, 12-1, 12-2, 12-3 (collectively referred to as MLCs 12). Each of the MLCs 12 is accessed by a corresponding bit line. For example, bit line 0 may control MLC 12-0 and bit line 1 may control MLC 12-1. Typically, a word line of MLCs may include a plurality of memory pages based on a number of bits per MLC. For example, a word line 14 includes two pages, page 0 and page 1, corresponding to the two-bit storage capacity of each of the MLCs 12.
Memory pages may be described by a corresponding bit significance (e.g., most significant, least significant, etc.). For example, page 0 may correspond to a most significant bit (MSB) in each of the MLCs 12, and page 1 may correspond to a least significant bit (LSB) in each of the MLCs 12. In other words, when one of the MLCs 12 stores a state “01,” the MSB (page 0) may be 0 and the LSB (page 1) may be 1.
MLC memory arrays are typically read or written using multiple pass (multi-pass) programming. In other words, one interleaved page of a word line may be read or written during each pass (i.e., R/W (read/write) cycle). For example, in word line 14, page 0 may be written during a first write pass and page 1 may be written during a second write pass.
Referring now to FIG. 2, an example of a memory IC 20 is shown. The memory IC 20 includes a MLC memory array 22, a bit line controller 24, a word line controller 26, and a control module 28. The MLC memory array 22 includes M rows and N columns including (M*N) MLC cells 30. The bit line controller 24 selects N columns of cells 30 via bit lines BL0-BL(N-1). The word line controller 26 selects M rows of cells 30 via word lines WL0-WL(M-1).
The control module 28 includes an address control module 32, a read/write (R/W) control module 34, and an error correction coding (ECC) module 36. The address control module 32 controls addressing of the cells 30 via the bit line controller 24 and the word line controller 26. The R/W control module 34 controls R/W operations of the cells 30. For example, the R/W control module 34 may perform multi-pass programming to write data to the cells 30. The ECC module 36 controls encoding of data written to the cells 30 and decoding (which may also include error correction) of data read from the cells 30.
The memory IC 20 communicates with a host 38 via a bus 40. The bus 40 includes address lines, data lines, and control lines. The host 38 issues R/W and control instructions to the memory IC 20 via the bus 40 when reading and writing data from and to the cells 30, respectively. The control module 28 reads and writes data from and to the cells 30 based on the R/W and control instructions.